This invention relates to sense amplifier circuits useful in CMOS integrated circuits and, more particularly, to regenerative amplifier circuits for quickly and correctly sensing small differential voltage signals.
A problem typically occurs when MOS regenerative sense amplifiers latch differential signals at high speed. For a typical MOS integrated circuit operating between V.sub.CC and ground, a fast NMOS latching operation may pull the sense amplifier input node with the high voltage signal down significantly, possibly as far down as V.sub.CC /2. This creates the possibility that the wrong side of the amplifier may conduct causing an erroneous output.
Furthermore, if the vagaries of semiconductor processing cause an imbalance in the physical parameters of the sense amplifier, the likelihood of improper conduction and latching increases. For example, imbalances in the transconductances, g.sub.m, or threshold voltages V.sub.T, of the cross-coupled transistors which typically form a latch in the sense amplifier, or in the capacitive loads of the inputs of the sense amplifier, could cause improper conduction and latching.
Imbalances in the initial differential signals itself may also cause problems in high speed latching. High speed sense amplifiers are typically used for reading static random access memory (SRAM) cells and imbalances in such memory cells themselves are possibilities.
The present invention solves or substantially mitigates such problems in high speed latching operations.